1. Field of the Invention
The present invention relates to a semiconductor device and a control method thereof, and more particularly relates to a semiconductor device in which an amplitude value of a voltage of an external data signal and an amplitude value of a voltage of an internal data signal are different from each other and a control method thereof. The present invention also relates to a data processing system that includes the semiconductor device.
2. Description of Related Art
In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a system for reducing power consumption is employed, in which an internal voltage that is lower than an external voltage is generated inside the semiconductor device and various peripheral circuits are operated with the internal voltage. In this case, because there is a difference between an amplitude value of a voltage of an internal signal and an amplitude value of a voltage of an external signal, it is necessary to insert a level shift circuit in a data path, thereby data is output to outside after converting the amplitude value of the internal voltage into the amplitude value of the external voltage.
As for a clock signal, although the amplitude value of the internal voltage is used in most peripheral circuits, a clock signal of which an amplitude value is converted into the amplitude value of the external voltage is required for a circuit portion that takes synchronization with data of which an amplitude value is converted into the amplitude value of the external voltage. Therefore, it is also necessary to insert a level shift circuit in a clock path for the clock signal, thereby the amplitude value of the clock signal is converted from the amplitude value of the internal voltage into the amplitude value of the external voltage.
For example, in FIG. 2 of U.S. Pat. No. 6,339,553, level shifters 130 and 135 are inserted right before a pulse generating circuit 160, which is a final stage of a DLL circuit 100, thereby an amplitude value of a voltage of an internal clock signal int.CLKP output from the DLL circuit 100 is converted into an amplitude value of an external voltage.
However, if the amplitude value of the voltage of the internal clock signal output from the DLL circuit is converted into the amplitude value of the external voltage as in the semiconductor device described in U.S. Pat. No. 6,339,553, it is not possible to fully achieve power consumption reducing effect, because all circuits that use an output of the DLL circuit have to be operated with the external voltage. Therefore, in order to further reduce the power consumption, it is required to further reduce the number of circuits that are operated with the external voltage by arranging the level shift circuit at a far latter stage.
An output circuit (an output buffer) is located at the last stage as a circuit for outputting data to outside. With the output circuit, it becomes possible to minimize the power consumption when all circuits prior to the output circuit are operated with the internal voltage and a level shift is performed within the output circuit.
However, in a semiconductor device of a type in which an output of data is performed in synchronization with both edges (a rising edge and a falling edge) of a clock signal, such as a DDR (Double Data Rate) SDRAM (Synchronous DRAM), if a level shift is performed within the output circuit, a skew occurs between output data synchronized with the rising edge and that synchronized with the falling edge. This is caused by the characteristics of the level shift circuit, which occurs because a delay amount of the rising edge and a delay amount of the falling edge are different from each other in a level shift operation.
Such a skew cannot be corrected even if the DLL circuit has a duty correction function, and the skew causes degradation of quality of the output data.